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JSSC 2022第10期Power ManagementPLLDLL

A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithe

提出一种基于标准单元的可合成分数N锁相环,采用DTC多级注入技术,降低抖动和功耗。
1.0095-GHz输出频率, 24-MHz参考频率, 2.55 ps RMS抖动, 3.36 mW功耗
分数N锁相环DTC多级注入抖动校准功耗优化
DTC多级注入技术减少DTC范围
抖动辅助局部偏移校准解决DCO级间失配
注入锁定和相位跟踪环路抑制抖动噪声
Abstract
A standard-cell-based fractional-N synthesizable phase-locked loop (PLL) [or multiplying-delay-locked loop (MDLL)] is proposed, where the multiple phases of the three- stage ring digitally controlled oscillator (DCO) are utilized for injection. The required digital-to-time converter (DTC) range is reduced to one third of the DCO’s period, resulting in higher linearity, less jitter, lower power consumption, and smaller area. The issue of the mismatches among DCO’s stages is solved by the proposed