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Arithmetic Progression Sw itched-Capacitor DCDC Converter Topology With Soft VCR
提出一种算术级数开关电容DC-DC转换器拓扑，实现软电压转换比和准对称两相电荷传输。
65nm CMOS, 1.5V输入, 0.18-1.19V输出, 400mA最大输出电流, 93.7%峰值效率
开关电容转换器电压转换比算术级数拓扑准对称电荷传输动态效率
▸采用算术级数开关电容拓扑实现系统化的可重构有理电压转换比
▸通过准对称两相电荷传输减轻输出电容需求
▸提出交叉耦合自举驱动电路，无需双分支交错架构
Abstract
This article presents an arithmetic progression (AP)
switched-capacitor (SC) dc–dc converter topology for systematic
step-down reconfigurable rational voltage conversion ratio (VCR)
generation while exhibiting soft VCR transitions and quasi-
symmetric two-phase charge delivery. The proposed AP topology
features fixed steady-state voltage in all the flying capacitors
(C
FLY) irrespective of VCR change, essentially eliminating the
internal CFLY hard-charging loss due to voltage rebalancing,
effective