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JSSC 2022第10期Data Converters65nmDelta-Sigma ADCDAC

Correlated Dual-Loop Sturdy MASH Continuous-Time Delta-Sigma Modulators

提出一种新型多环路ΔΣ调制器结构,结合MASH和SMASH优势,消除量化误差提取DAC需求。
65nm CMOS, 1.1/1.5V, 600MHz, 73.4dB SNDR, 78.3dB DR, 17.85mW
ΔΣ调制器多环路结构MASHSMASH量化误差
结合传统MASH和SMASH架构优势
消除多环路结构中显式量化误差提取DAC需求
简化结构,移除级联环路中所有反馈DAC
Abstract
This article presents a new multi-loop delta-sigma modulator (DSM) structure that combines the advantages of both the traditional multi-stage noise shaping (MASH) and sturdy MASH (SMASH) architectures. It removes the need for an explicit quantization error extraction digital-to-analog converter (DAC) typically required in multi-loop structures, which allows to eliminate the delay mismatch problem related to the intrinsic propagation delay of the first loop quantizer. The proposed architecture essentially uses the SMASH architecture as its core and has similar characteristics. However, it further simplifies the structure allowing to remove all the feedback DACs in the cascaded loop. The prototype DSM fabricated in a 65-nm process achieves signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) of 73.4 and 78.3 dB, respectively, in an 18.75-MHz bandwidth. With 1.1/1.5-V (1.5 V for DAC) supply voltage, the prototype DSM consumes 17.85 mW at 600-MHz operating speed corresponding to a Walden and Schreier figure of merits (FOMs) of 124.1 fJ/conv-step and 168.6 dB (using DR result), respectively.