A 10-GS/s 8-bit 2850- μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC

Abstract

This article presents an 8-bit time-domain analog- to-digital converter (ADC) achieving ten-GS/s conversion speed with only two time-interleaved (TI) channels. A successive approximation register (SAR) time-to-digital converter (TDC) is implemented for the subpicosecond resolution time quantization with high power/area efficiency and low jitter. The throughput of the SAR TDC is enhanced by a unique delay-tracking pipelining technique to enable a 5-GS/s single-channel conversion. On the circuit level, the reference time generation for the SAR TDC is realized by the proposed selective delay tuning (SDT) cell for high efficiency and small reference time variation. Fabricated in the 14-nm FinFet CMOS technology, this ADC achieves a 37.2-dB signal-to-noise and distortion ratio (SNDR) and a 50.6-dB spurious-free dynamic range (SFDR) at the Nyquist input frequency, leading to a 24.8-fJ/conv-step Walden figure of merit with an active area of only 2850 µm 2.