A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS

Abstract

This article presents a 5-GS/s continuous-time (CT) multi-stage noise-shaping (MASH) analog-to-digital converter (ADC). The ADC consists of three first-order modulators with a 3-bit quantizer/digital-to-analog converter (DAC) per stage. An RC-hybrid stabilization DAC is used to compensate for the excess loop delay and excess phase shift. A delay matching all- pass input filter with a low-pass feedforward filter is employed to suppress input signal leakage. As a result, inter-stage DACs are waived in residue generation, and low-power, area-saving Gm-C integrators are enabled in the back-end stages. The MASH ADC was implemented in 40-nm CMOS and occupies 0.21 mm 2.T h e ADC achieves 68-dB dynamic range (DR) and 65-dB signal-to- noise and distortion ratio (SNDR) over a 360-MHz bandwidth (BW). The ADC consumes 158 mW from 1/1.1/1.8 V supplies, yielding 159-dB Schreier figure-of-merit (FOM) and 151-fJ/Conv. Walden FOM.