JSSC 2022第12期Data Converters28nmSAR ADC

A 72-dB SNDR 130-MSs 08-mW Pipelined-SAR ADC Using a Distributed Averaging Corre

一种采用分布式平均相关电平移位技术的14位130MS/s流水线-SAR ADC，具有高SNDR和低功耗。

28nm CMOS, 130MS/s, 72.5dB SNDR, 0.82mW

流水线-SAR ADC分布式平均相关电平移位环形放大器旁路窗口低功耗

▸分布式平均相关电平移位（DACLS）环形放大器，无需额外电平移位电容，提高带宽

▸定制化旁路窗口方案，减少DAC切换功耗

▸延迟减少（DR）SAR逻辑，提升转换速度

Abstract

This article presents a 14-b 130-MS/s two-stage pipelined-SAR analog-to-digital converter (ADC) using a distrib- uted averaging correlated level shifting (DACLS) ring ampliﬁer as its residue ampliﬁer (RA). Compared to the prior CLS and ACLS techniques that reduce the RA gain error due to their ﬁnite open-loop gain, the proposed DACLS ring ampliﬁer no longer requires an extra level-shifting capacitor ( C LS) at the RA output, such that the RA bandwidth can be improved. Furthermore, instead of a s