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A Fractional- N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time Simone M. Dartizio
提出一种基于II型齿轮切换和自适应频率切换的快速锁定、低抖动分数-N Bang-Bang锁相环。
28nm CMOS, 0.23 mm², 1.56 µs锁定时间, 48.6 fs rms抖动, 20 mW功耗
分数-N锁相环Bang-Bang锁相环II型齿轮切换自适应频率切换低抖动
▸创新点1：II型齿轮切换技术（Type-II Gear Shifting）通过优化PLL频率瞬态过程，避免了传统BBPLL中的极限环问题，显著缩短了锁定时间至1.56 µs以内（80 ppm精度），属于系统级创新。
▸创新点2：自适应频率切换技术（AFS）利用现有硬件资源动态调整频率误差，在通道切换时减少PLL频率偏差，实现8.5–10 GHz范围内1.5 GHz跳频的快速响应，属于电路级创新。
▸创新点3：通过协同优化抖动与锁定时间的矛盾关系，在28nm CMOS工艺下实现48.6 fs（整数通道）和68.6 fs（分数通道）的超低RMS抖动，同时保持20mW低功耗，属于性能指标突破。
▸创新点4：集成型架构设计将主动区面积压缩至0.23mm²，并结合分数-N分频实现-58.2dBc的杂散抑制，体现了混合信号电路设计的方法创新。
Abstract
This work presents a fast-locking and low-jitter fractional-N bang-bang phase-locked loop (BBPLL). To break the trade-off between jitter and locking time which is typical of BBPLLs, two novel techniques are introduced. A gear-shift technique, denoted as type-II gear-shift, avoids limit cycles in the phase-locked loop (PLL) frequency transient and optimizes the locking time of the main PLL loop. The adaptive frequency switching (AFS) technique reduces the PLL frequency error upon channel switching exploiting the already existing hardware. The prototype, implemented in a 28-nm CMOS process, has an active area of 0.23 mm 2 and achieves a locking time always below 1.56 µs (within 80 ppm accuracy) for frequency jumps up to 1.5 GHz over the 8.5–10 GHz tuning range. The measured rms jitter (integrated from 1 kHz to 100 MHz) is 48.6 fs for integer-N channels and 68.6 fs for near-integer fractional- N channels, with a worst case fractional spur of −58.2 dBc. The power consumption is 20 mW, leading to a jitter-power figure of merit of −253.2 and −250.3 dB for integer- N and fractional- N channels, respectively.