JSSC 2022第12期Power Management65nmPLL

A Low-Jitter Ring-DCO-Based Fractional- N Digital PLL With a 18 DTC-Range-Reduct

提出一种基于环形振荡器的低抖动分数-N数字锁相环，通过减少DTC热噪声和动态选择相位降低抖动。

65nm CMOS, 0.139mm², 15.67mW, 5.2GHz, 188fs rms jitter, -243dB FoM

数字锁相环环形振荡器数字时间转换器低抖动分数-N

▸四倍时序裕度相位选择器(QTM-PS)降低DTC动态范围和热噪声

▸双沿发生器(DEG)加倍DPLL带宽抑制RO抖动

▸集成背景校准器(IBC)通过LMS校准确保QTM-PS和DEG稳定性

Abstract

This work presents a fractional- N ring-oscillator (RO)-based digital phase-locked loop (DPLL). To achieve ultralow jitter, the proposed RO-DPLL used a technique to reduce the dominant source of in-band noise, i.e., the thermal noise of the digital-to-time converters (DTCs). A key building block of this technique is the quadruple-timing-margin phase selector (QTM-PS) that dynamically selects the proper phase among the eight phases of the RO, effectively reducing the required dynamic range of the