← 返回 JSSC 论文列表JSSC 2022第12期RF & Wireless65nmSAR ADCNeural Network Accelerator
An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRF
提出一种低过采样率高分辨率四阶噪声整形SAR ADC，结合EF-CRFF结构和BIL技术。
65nm CMOS, 1.2V/2V, 500kHz BW, OSR=5, 84.1dB SNDR, 133.8μW
噪声整形SAR低过采样率EF-CRFF结构缓冲器环路高分辨率ADC
▸创新的误差反馈-级联谐振器前馈（EF-CRFF）结构
▸噪声抑制的缓冲器环路（BIL）技术
▸高能效与鲁棒性平衡设计
Abstract
To design a low-oversampled high-resolution noise-
shaping successive approximation register (NS-SAR) analog-to-
digital converters (ADCs), two main bottlenecks need to be
addressed. One is to implement high-order optimized NS with
simple and low-power hardware that maximally preserves a
SAR’s efficient nature, and the other is to alleviate the sam-
pling noise and input driving burden. This article presents a
fourth-order NS-SAR ADC that synergistically addresses both
challenges. It proposes an