JSSC 2022第12期Clocking & PLLs55nm

Ultra-Low Phase Noise X-Band BiCMOS VCOs Leveraging the Series Resonance Alessan

本文提出一种利用串联谐振降低X波段BiCMOS VCO相位噪声的新电路拓扑。

55nm BiCMOS, 1.2V, 10GHz, -138dBc/Hz@1MHz, -190dBc/Hz FoM

超低相位噪声X波段BiCMOSVCO串联谐振

▸电路创新：通过利用串联谐振显著降低谐振器阻抗，从而在不显著降低品质因数的前提下，大幅提升谐振器的有功功率，有效降低相位噪声。

▸方法创新：提出了一种新的电路拓扑结构，突破了传统并联谐振振荡器的相位噪声限制，通过串联谐振实现更高的功率效率，无需大幅缩小电感尺寸。

▸性能创新：设计的BiCMOS VCO在10 GHz中心频率下实现了超低相位噪声，达到-138 dBc/Hz @ 1 MHz，并具有优异的FoM值-190 dBc/Hz，创下硅基集成振荡器的最低相位噪声记录。

▸系统创新：通过不同的谐振器实现方式，扩展了频率调谐范围并优化了功耗与相位噪声的权衡，实现了16%的调谐范围和-133 dBc/Hz @ 1 MHz的相位噪声。

Abstract

The most effective way to reduce phase noise in integrated harmonic oscillators is by rising the active power in the resonator, i.e., scaling down the tank impedance and increasing power consumption. However, in widespread parallel- tank oscillators, a lower bound is readily set by the smallest inductance that can be implemented without incurring into excessive degradation of the quality factor. Emerging multicore oscillators circumvent the issue only partially. In this article, a cir- cuit topo