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A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface Jong Hak Y uh , Y en-Lung Jason Li, Heguang Li, Y oshihiro Oyama, Cynthia Hsu, Pradeep Anantula, Gwang Y eong Stanley Jeong, Anirudh Amarnath, Siddhesh Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex Y ap, Demin Wang, Steve Kim, Y onggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, Taekeun Han, Masatoshi Okumura, Jiwen Liu , Jeongduk John Sohn, Hardwell Chibvongodze, Muralikrishna Balaga, Akihiro Matsuda, Chen Chen , Indra K. V ., V . S. N. K. Chaitanya G., V enky Ramachandra, Y osuke Kato, Ravi J. Kumar, Huijuan Wang, Farookh Moogat, In-Soo Y oon, Kazushige Kanda, Takahiro Shimizu, Noboru Shibata, Kosuke Y anagidaira, Takuyo Kodama, Ryo Fukuda
1Tb 4位/单元162层3D闪存,采用中央阶梯结构和CTW架构,实现15Gb/mm²面密度和60MB/s编程吞吐量。
15Gb/mm²面密度,60MB/s编程吞吐量,65µs最佳tR,2.4Gb/s IO速度
3D闪存高密度存储IO接口功耗管理数据总线反转
▸创新点1:8kB字线中央阶梯结构(系统创新) - 通过采用8kB字线中央阶梯结构,显著提高了存储密度和编程吞吐量,实现了15-Gb/mm2的面积密度和60 MB/s的编程吞吐量,优化了存储单元布局。
▸创新点2:接触穿字线(CTW)架构(电路创新) - CTW架构通过减少层间连接复杂度,提升了信号传输效率,降低了延迟,最佳情况下tR达到65 µs,同时支持2.4 Gb/s的IO速度。
▸创新点3:时间分割峰值功耗管理(TD-PPM)(系统创新) - 通过时间分割峰值功耗管理技术,有效降低了系统峰值电流,同时最大化系统性能,提升了能效比,适用于高密度存储应用。
▸创新点4:VCCQ域设计与数据总线反转(DBI)技术(电路创新) - 采用VCCQ域设计和DBI技术,显著降低了数据传输能耗,提升了能效,适用于高速IO接口(24-Gbs)。
Abstract
A 1 Tb 4-b/cell 162-layer 3-D flash memory achieves 15-Gb/mm2 areal density and delivers program throughput up to 60 MB/s and the best case tR of 65 µs by employing 8-kB wordline (WL) central stair structure and contact-through-WL (CTW) architecture. IO speed of 2.4 Gb/s with low tapped termination/center tapped termination (LTT/CTT) combo driver is supported. This article also discusses data transfer energy reduction using VCCQ domain design and data bus inver- sion (DBI) technique. Novel time division peak power manage- ment (TD-PPM) feature can reduce system peak current while maximizing system performance. Cache and IO discrete Fourier transform (DFT) enable a high-speed testing at wafer level for test cost reduction.