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A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ Daewoong Lee , Associate Member , IEEE, Jaehyeok Baek, Hye-Jung Kwon, Dae-Hyun Kwon, Chulhee Cho , Associate Member , IEEE, Sang-Hoon Kim, Donggun An , Chulsoon Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun-Y oung Park, Hyoung-Joo Kim, Hoseok Seol, Juhwan Kim, Jungbum Shin, Gil-Y oung Kang, Y ong-Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, Chan-Y ong Lee, Seungseob Lee, Tae-Hoon Park, Chi-Sung Oh , Hyodong Ban
首款采用T-coil技术的16Gb GDDR6 DRAM，通过合并多路复用器TX和优化WCK操作实现27Gb/s/pin带宽
27 Gb/s/pin with 1.35 V
GDDR6T-coilDRAM带宽优化数据时钟
▸首次在DRAM工艺中实现T-coil技术
▸采用合并多路复用器(TX)优化数据传输
▸使用替代数据总线(ADB)解决数据总线频率限制
Abstract
This article introduces a 16-Gb T-coil-based
graphics double-data-rate 6 (GDDR6) dynamic random access
memory (DRAM) with merged-multiplexer (MUX) transmitter
(TX), optimized data clock (WCK) operation to enhance I/O
bandwidth. T-coil is implemented for the first time in a DRAM
process. Moreover, an alternative-data-bus (ADB) is employed to
solve the frequency limit of the data bus. The proposed T-coil-
based GDDR6 DRAM achieves 27 Gb/s/pin with 1.35 V in a
DRAM process.