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A 56-GHz Fractional- N PLL With 110-fs Jitter Yu Z h a o Member IEEE Onur Memi
一种采用28nm CMOS工艺的56GHz分数N锁相环，具有110fs抖动和低相位噪声。
56GHz, 110fs抖动, -98dBc/Hz@1MHz, 23mW功耗, 0.1mm²面积
分数N锁相环FIR滤波器ΔΣ调制器低相位噪声CMOS
▸采用开关电流FIR滤波器抑制ΔΣ调制器噪声
▸紧凑低功耗的8分频电路
▸在分数N模式下实现-98dBc/Hz的相位噪声
Abstract
A fractional- N phase-locked loop (PLL) architec-
ture incorporates a switched-current finite impulse response
(FIR) filter to suppress the /Delta1/Sigma1modulator ( /Delta1/Sigma1M) noise. Using
a compact, low-power divide-by-8 circuit and realized in 28-nm
CMOS technology, the PLL exhibits a phase noise of −98 dBc/Hz
at 1-MHz offset in the fractional- N mode while consuming
23 mW and occupying an active area of 0.1 mm
2.