A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68

Abstract

This work presents an ultralow-jitter ring-oscillator (RO)-based injection-locked clock multiplier (ILCM). Using the power-gating (PG) injection method that can completely remove the accumulated phase error of the RO, the proposed ILCM can achieve a very wide injection bandwidth, and, thus, an ultralow- jitter, even when the multiplication factor, N,i si n c r e a s e d above 60. To overcome the natural limitation of the PG injection, two digitally controlled oscillators (DCOs) were used to operate in a complementary manner. Since the background multi-functional calibrator (MFC) continuously synchronizes the outputs of the two DCOs, the PG-ILCM can generate a seamless output signal by combining these two signals. The proposed injection pulsewidth controller (IPWC) decreased the required delay of the digital-to-time converter (DTC), further reducing the jitter of the output signal. A phase-rotational divide-by-4 divider (PR-DIV4) also was proposed to reduce the operating frequency and the power consumption of the MFC while maintaining the fine resolution of the output frequency. The PG-ILCM, fabricated in a 65-nm CMOS process, used the power of 14.3 mW and an area of 0.102 mm 2. The rms jitter measured at 8.16 GHz (N = 68) was 97 fs.