← 返回 JSSC 论文列表JSSC 2023第1期Clocking & PLLs65nm
A Sub-100 fs-Jitter 816-GHz Ring-Oscillator-Based Power-Gating Injection-Locked
提出一种基于环形振荡器的超低抖动注入锁定时钟乘法器,采用功率门控注入方法实现宽注入带宽和低抖动。
65nm CMOS, 14.3mW, 0.102mm², 97fs rms jitter at 8.16GHz
环形振荡器注入锁定功率门控超低抖动时钟乘法器
▸功率门控注入方法消除环形振荡器累积相位误差
▸互补工作的数字控制振荡器克服功率门控限制
▸背景多功能校准器实现无缝输出信号
Abstract
This work presents an ultralow-jitter ring-oscillator
(RO)-based injection-locked clock multiplier (ILCM). Using the
power-gating (PG) injection method that can completely remove
the accumulated phase error of the RO, the proposed ILCM can
achieve a very wide injection bandwidth, and, thus, an ultralow-
jitter, even when the multiplication factor, N,i si n c r e a s e d
above 60. To overcome the natural limitation of the PG injection,
two digitally controlled oscillators (DCOs) were used to oper