JSSC 2023第1期Digital CircuitsProcessor/CPU

Deterministic Frequency and V oltage Enhancements on the POWER10 Processor Brian

POWER10处理器通过数字下垂传感器和核心节流技术提升频率并降低电压。

15%频率提升，10%核心电压降低

数字下垂传感器核心节流电压控制回路工作负载优化频率POWER10处理器

▸数字下垂传感器（DDS）与核心节流技术

▸电压控制回路（欠压）抵消负载线提升和噪声效应

▸运行时算法实现工作负载优化频率（WOF）

Abstract

Digital droop sensors (DDSs) with core throttling mitigate microprocessor voltage droops and enable a voltage control loop (undervolting) to offset loadline uplift plus noise effects, protecting reliability V DDMAX . These combine with a runtime algorithm for workload optimized frequency (WOF) that deterministically maximizes core frequency. The combined effect is demonstrated across a range of workloads, including SPEC, and provides up to a 15% frequency boost and a 10% reduction in core voltag