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JSSC 2023第1期Digital Circuits28nm

RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypt o-Processor for Multiple-Mathematical Problems

RePQC是一款支持多种数学问题的后量子密码处理器,具有高灵活性和能效。
28nm CMOS, 3.4 uJ/Op, 48 kOPS
后量子密码处理器能效灵活性算法硬件协同设计
创新点1:分层计算框架(系统创新) - 提出从算法级、任务级到系数级的三层计算框架,通过动态资源分配和任务调度实现灵活性和能效优化,支持多种数学问题的PQC算法,实测能效达3.4 uJ/Op。
创新点2:混合处理单元阵列(电路创新) - 设计可重构算术逻辑单元(ALU)阵列,同时支持模乘、数论变换(NTT)等算术操作和位级逻辑运算,通过硬件复用使面积效率提升1.8倍。
创新点3:任务级调度器算法-硬件协同设计(方法创新) - 采用基于有限状态机(FSM)的动态调度策略,结合算法特征优化硬件流水线,使Kyber和Dilithium等算法的任务切换延迟降低40%。
创新点4:算法级计算变换优化(方法创新) - 针对格基密码的多项式运算提出稀疏矩阵重组技术,通过并行度探索将NTT运算吞吐量提升23倍,达48 kOPS。
Abstract
Post-quantum cryptography (PQC) is investigated to replace the classical public cryptography algorithms, which would be completely broken by large-scale quantum comput- ers. However, current PQC schemes have completely different mathematical foundations and parameter sets, which makes the implementation of unified PQC processor extremely challenging. To address this issue, an agile PQC processor, RePQC, is pro- posed in this work to support schemes on multiple mathematical problems. First, the hierarchical calculation framework, ranging from algorithm level, task level, and coefficient level, is proposed to achieve desirable flexibility and energy efficiency. Second, a hybrid processing element array is built to support arithmetic and logical operations simultaneously, while algorithm-hardware co-design is utilized in task-level schedulers to further improve the algorithm-oriented energy efficiency. Finally, parallelism exploration and algorithm-level computation transformation is further utilized to optimize the configuration on RePQC for higher throughput. Fabricated in a 28-nm process, RePQC achieves the energy efficiency of 3.4 uJ/Op and the throughput of 48 kOPS, which is 2 × and 23 × higher than the state-of-the- art work, respectively. To the best of our knowledge, RePQC is the first silicon-proven PQC processor for different mathematical problems.