← 返回 JSSC 论文列表JSSC 2023第2期Digital Circuits40nm
A 40-nm 91-mW 90-fps Learning-Based Full HD Super-Resolution Accelerator Hsueh-Y
40纳米工艺下91毫瓦功耗的90帧/秒全高清超分辨率加速器
40nm CMOS, 200MHz, 90fps, 91mW
超分辨率神经网络加速器内存调度内核压缩
▸内存调度方案提高低分辨率上采样器利用率50%
▸内核压缩减少片上内存72%
▸补丁重用方案减少外部内存访问次数91%
Abstract
Super-resolution has been utilized in a plenty of
applications to provide better visual experience. To meet the
high-throughput and low-power n eeds, some dedicated accelera-
tors for super-resolution have been proposed. Neural-network
(NN)-based super-resolution accelerators achieve impressive
restoration performance, but the high-computational complexity
does not allow a high throughput for video streaming. This
work presents a super-resolution accelerator that implements the
rapid and accurat