JSSC 2023第3期Data Converters40nmSAR ADC

A 13b 600-675MS-s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Resi

一款采用三态SAR逻辑和开环逆变器残差放大器的13位高速流水线-SAR ADC。

40nm CMOS, 1.1-1.2V, 600-675MS/s, 62.8dB SNDR, 7.05mW

流水线-SAR ADC三态SAR逻辑开环残差放大器比较器亚稳态高速ADC

▸利用比较器亚稳态实现三态SAR逻辑，加快逼近过程

▸提出开环逆变器残差放大器，增益由gm比定义，抗PVT变化

▸亚稳态边界设置为±1/4 LSB时，ENOB可提升1位

Abstract

This article presents a 13-b high-speed pipelined- successive-approximation-register (pipelined-SAR) analog- to-digital converter (ADC). By utilizing the comparator metastability, a tri-state SAR logic is introduced to achieve a fast approximation process. The tri-state SAR outputs three states by one comparator after each comparison cycle, and the effective-number-of-bits (ENOBs) can improve up to 1 b when the metastability boundary is set at ±1/4 LSB. In addition, an open-loop inverter-based r