JSSC 2023第3期Data Converters65nmSAR ADCDelta-Sigma ADC

A 20--s Turn-On Time- 24-kHz Resolution- 15-100-MHz Digitally Programmable Tempe

提出一种基于快速锁定频率锁定环和Δ-Σ分数分频器的可编程温度不敏感时钟发生器

1.5–100 MHz可编程频率范围, 24-kHz分辨率, 140-ps峰峰值周期抖动, 6.8-ppm/°C温度不敏感性

时钟发生器频率锁定环Δ-Σ分数分频器温度不敏感快速启动

▸使用SAR逻辑加速FLL锁定

▸采用截断误差消除技术降低Δ-Σ抖动

▸实现快速启动（20μs）和高分辨率（24kHz）

Abstract

A clock generator using a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs) to generate programmable temperature-insensitive output frequencies is presented. Successive approximation register (SAR) logic is used to speed up the locking of the FLL, and truncation error cancellation (TEC) is performed in FDIVs to reduce delta- sigma-induced jitter. A prototype clock generator fabricated in a 65-nm CMOS process generates output clocks in the ra