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A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital P
提出一种低抖动、低带外噪声的双核分数-N数字PLL，采用新技术优化功耗与噪声。
28nm CMOS, 0.47mm², 8.5-10.5GHz, 36mW, 72fs抖动, -59.7dBc杂散
分数-N数字PLL双核架构低抖动量化噪声抑制带外噪声
▸数字周期平均技术抑制DCO量化噪声
▸真同相组合器电路优化PLL噪声源影响
▸双核架构实现功耗与噪声的最佳平衡
Abstract
This work presents a low-jitter and low out-of-
band noise two-core fractional- N digital bang-bang phase-locked
loop (PLL). Two novel techniques are introduced to efficiently
suppress the quantization noise (QN) of the digitally controlled
oscillator (DCO) and to achieve an optimal trade between power
consumption and PLL noise. The digital period averaging tech-
nique, working in background of the main system, enables the use
of a low-power
XOR -based quadrupler for clocking /Delta1/Sigma1modula