A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET Yu a n m i n g Z h u, Member , IEEE

Abstract

Demand for increased data rates in serial link transceivers calls for innovative architectures capable of over- coming impairments such as limited channel bandwidth (BW) and stringent jitter specifications. This article presents a receiver front-end (RXFE) architecture that supports multicarrier signal- ing to provide a ∼3× relaxation in clock jitter requirements. A total of 40 Gb/s data rate is supported by three 4-GS/s bands with baseband (BB) four-level pulse amplitude modula- tion (PAM4) and mid-band (MB) and high-band (HB) 16-state quadrature amplitude modulation (QAM16) on 4- and 8-GHz orthogonal carriers, respectively. The RXFE uses three per-band optimized continuous-time linear equalizers (CTLEs) to par- tially equalize the in-band channel loss and four-way time- interleaved 7-b pipelined-successive approximation register (SAR) analog-to-digital converters (ADCs). Tight band spac- ing is achieved with tolerable inter-channel interference (ICI) using resettable integrators in the receiver segments. Fab- ricated in a 22-nm fin field-effect transistor (FinFET), the proposed 40-Gb/s multicarrier RXFE can tolerate up to 1.6-ps rms jitter and achieve a bit error rate (BER) < 10−5 oper- ating over a channel with 20-dB loss at 10 GHz when combined with an off-chip one-tap digital ICI canceller. The ADC-based front-end achieves 3.05-pJ/bit power efficiency, including all the front-ends, ADC, and clocking power.