JSSC 2023第4期Data Converters65nmSAR ADC

A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Ampliﬁer Hyunchul Y oon

提出一种PVT鲁棒的电容退化动态放大器，用于低功耗流水线SAR ADC，实现65dB SNDR和79.8dB SFDR。

65nm CMOS, 0.8-1.0V, 50MS/s, 65dB SNDR, 79.8dB SFDR, 0.46mW

PVT鲁棒电容退化动态放大器流水线SAR ADC低功耗时序发生器

▸创新点1：采用PVT鲁棒的电容退化动态放大器作为残差放大器，通过优化电容退化结构显著提升温度稳定性，在0°C-100°C范围内SNDR仅变化1.86dB（电路创新）

▸创新点2：提出两阶段动态放大器架构，在保持高线性度和宽输出摆幅的同时实现16倍电压增益，解决了传统动态放大器增益不足的问题（架构创新）

▸创新点3：集成低功耗片上时序发生器，仅消耗总功耗的10%，有效控制放大器工作时序并降低系统整体功耗（系统级创新）

▸创新点4：在65nm CMOS工艺下实现0.46mW超低功耗，同时达到65dB SNDR和79.8dB SFDR的高性能指标，展现卓越的能效比（性能创新）

Abstract

This article presents a process, voltage, and temper- ature (PVT)-robust capacitively degenerated dynamic ampliﬁer as the residue ampliﬁer of the low-power pipelined successive- approximation-register (SAR) analog-to-digital converter (ADC). The proposed dynamic ampliﬁer achieves a voltage gain of 16 with a two-stage conﬁguration and high linearity over a wide temperature range with an on-chip timing generator. This work solves problems related to the low voltage gain and high temperature–sensitivity of the capacitively degenerated dynamic ampliﬁer, while retaining the advantages of high linearity, wide output swing, and high energy efﬁciency. The prototype ADC is implemented in a 65-nm CMOS process and achieves 65-dB signal-to-noise-and-distortion ratio (SNDR) and 79.8-dB spurious free dynamic range (SFDR) at a sampling rate of 50 MS/s, while consuming only 0.46 mW. The power overhead of the timing generator is only 10% of the overall power consumption. It shows only 0.7-dB and 1.86-dB SNDR variations at 0.8–1.0-V s upply variation and 0 ◦C–100 ◦C temperature variation, respectively.