A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links Timothy O. Dickson , Senior Member , IEEE, Zeynep

Abstract

This article details the design and measurement of a digital-to-analog converter (DAC)-based source-series terminated (SST) transmitter (TX) for wireline applications in 4-nm FinFET CMOS technology. The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture along with a single-ended LSB. Strength adjustment of the lower four DAC LSBs relative to the upper four DAC MSBs is accomplished with a hybrid analog/digital tuning approach, which overcomes minimum device-size limitations that can limit the effectiveness of pure digital tuning for SST drivers. The resulting DAC design achieves well-matched MSB/LSB segments with −0.63/0.67 LSB integral nonlinearity (INL) and −0.16/0.43 LSB differential non- linearity (DNL). Time-domain modulation of 216-Gb/s PAM8 and frequency-domain modulation of 212-Gb/s orthogonal frequency- division multiplexing (OFDM) are reported, demonstrating the capability of CMOS DACs to support frequency-domain modu- lation for wireline applications. The TX consumes 288 mW from a 0.95-V power supply.