JSSC 2023第4期Clocking & PLLs65nmDLLNeural Network Accelerator

A V ery High Linearity Twin Phase Interpolator With a Low-Noise and Wideband Del

提出一种高线性度双相位插值器，结合低噪声宽带延迟锁相环，实现3.5-11GHz频段内的高精度时钟生成。

1.2V 65nm CMOS, 7GHz, 7.8mW, 48.1fs rms jitter, -257.4dB FoM

相位插值器延迟锁相环正交时钟低噪声宽带

▸双相位插值器架构消除确定性相位非线性

▸Delta QDLL生成宽带低抖动正交时钟

▸背景模拟正交调谐环路提高精度

Abstract

A twin phase-interpolator (PI) architecture cancels most of the deterministic phase nonlinearity and achieves very high linearity across a wide frequency range with only four-phase input clocks. A delta quadrature delay-locked loop (Delta QDLL) is further proposed that genera tes wideband, low-jitter, and accurate quadrature clocks from the delay difference of two paths with a background analog quadrature tuning loop. A 1.2-V 65-nm CMOS prototype has a Delta QDLL with a quadrature accuracy of 0.