← 返回 JSSC 论文列表JSSC 2023第4期Other28nmSAR ADCDelta-Sigma ADC
An 816 dB SNDR 15625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noi
本文提出了一种时间交织架构，解决了连续时间ΣΔ调制器中噪声整形SAR量化器的速度-分辨率瓶颈问题。
28nm CMOS, 6.4mW功耗, 0.072mm²面积, 15.625MHz带宽, 81.6dB SNDR
连续时间ΣΔ调制器噪声整形时间交织SAR量化器数据加权平均
▸时间交织架构实现噪声整形量化器的完全并行化
▸延迟引入反馈环路实现高量化器分辨率
▸数据加权平均技术消除校准需求
Abstract
This work introduces a time-interleaved architec-
ture to tackle the speed-resolution bottleneck of the noise-shaping
(NS) successive approximation register (SAR) quantizer in a
continuous-time (CT) sigma-delta modulator (SDM). A critical
insight is that introducing a delay in the NS quantizer feedback
loop enables complete parallelization of the NS quantizer oper-
ations. The extra time from parallelization greatly relaxes loop
filtering and residue integration and enables a high quantizer
resol