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An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMO
八核RISC-V处理器在末级缓存附近进行乘加运算，显著降低能耗。
1.15-GHz, 52×能效提升(全连接层), 29×能效提升(卷积层), 4.25×延迟降低
RISC-V末级缓存计算乘加运算能效优化神经网络加速
▸在末级缓存(LLC)附近进行乘加(MAC)运算
▸支持512位宽内存访问指令
▸减少数据移动并保持操作数本地化
Abstract
An eight-core 64-b processor extends RISC-V to
perform multiply–accumulate (MAC) within the shared last
level cache (LLC). Instead of moving data from the LLC to
the core, compute near last level cache (CNC) adds MAC to
the LLC datapath and performs computation near where the
data are stored. The RV64GC CNC instruction set architecture
(ISA) extension performs digital MAC near unmodified SRAM
arrays and has a low area overhead of 1.4%. CNC increases
memory access width to 512 b per instruction by