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Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology Y usung
基于Intel 4 CMOS工艺的高能效高带宽6T SRAM设计
0.0300-µm² SRAM单元, 访问能耗降低>80%, 宏密度提升30%
6T SRAM高带宽能效优化Intel 4工艺存储器设计
▸创新点1：列多路复用技术(CM=1)，通过减少列选择电路的复杂度，显著降低了访问能量，同时提高了阵列的访问带宽。
▸创新点2：飞位线(FBL)技术，通过优化位线布局，减少了位线电容，从而降低了动态功耗，提升了SRAM的能效。
▸创新点3：被动写入辅助方案，采用无源电路设计，有效降低了写入操作的能量消耗，同时保持了写入稳定性。
▸创新点4：能量高效列设计，通过优化列驱动电路和位线预充电策略，进一步降低了整体能量消耗，提升了SRAM的能效比。
Abstract
In this article, we present an energy-efficient high
bandwidth array design using 0.0300- µm2 high-performance
SRAM bitcell on Intel 4 CMOS technology. By employing a
unique combination of design techniques–column mux (CM)
of 1, flying BL (FBL), passive write assist scheme, and
energy-efficient column design–the proposed 6T SRAM array
design demonstrates >80% access energy improvement over a
conventional four-way interleaved 6T SRAM array design and
30% macro density improvement compared to a hiera