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Ultra-Low-Power and Compact-Area Analog Audio Feature Extraction Based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification
提出超低功耗和小面积模拟音频特征提取芯片，用于关键词识别。
65nm CMOS, 80nW, 0.53mm²
超低功耗模拟音频特征提取时间模式关键词识别
▸创新点1：时间模式模拟滤波器组插值 - 该方法创新性地利用数字XOR门对模拟带通滤波器组输出进行插值，将输出通道数量翻倍，显著提高了特征提取的频域分辨率，同时保持低功耗（80 nW）和小面积（0.53 mm²）。
▸创新点2：时间模式模拟整流 - 该电路创新采用单个数字XOR门实现全波整流功能，相比传统模拟整流电路大幅降低了面积和功耗，是首个将纯数字门用于模拟信号整流的方案。
▸创新点3：超低功耗系统架构 - 系统级创新通过时间模式ASP技术统一处理模拟和数字域信号，实现整体功耗仅80nW（18倍优于前代），同时维持>90%的十关键词分类准确率。
▸创新点4：混合信号集成技术 - 在65nm LP CMOS工艺中创新性地整合时间模式模拟处理与数字逻辑，达成0.53mm²超紧凑面积（3.3倍优于前代），突破传统模数分离设计的面积限制。
Abstract
To address the power and area bottleneck imposed by the frontend feature extractor relative to the backend neural network in on-device keyword spotting (KWS), we propose two time-mode analog signal processing (ASP) circuit techniques showcased in an analog audio feature extractor chip that advances the state of the art in power- and area-efficiency. Time- mode analog filterbank interpolation uses digital XOR gates to double the number of outputs of an analog bandpass filterbank. Time-mode analog rectification uses a single digital XOR gate as an analog full-wave rectifier. The 65 nm low power (LP) CMOS chip uses only 80 nW and 0.53 mm 2 to extract from an input analog audio signal, an output digital auditory feature vector with 31 elements. This represents 18× and 3.3× improvements in power/feature and area/feature, as compared, respectively, to the most area- and power-efficient published analog audio feature extractor chips. All the while, competitive classification accuracy is maintained at >90% across ten