A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

Abstract

This article presents a 48-Gb/s four-level pulse amplitude modulation (PAM-4) receiver with a Baud-rate clock and data recovery (CDR) suitable for multi-level signaling. By deriving the relation between the vertical eye margin (VEM) and the ratio of main-cursor to pre-cursor, the proposed Baud- rate phase detector (BRPD) adjusts the pre-cursor and finds the lock point with targeted vertical eye opening. Thus, the BRPD offers a unique lock point when used with an adaptive decision feedback equalizer (DFE) where post-cursor h 1 is removed. Otherwise, the lock point could drift with the conventional Mueller–Müller phase detector (PD). Furthermore, a summer loading of the DFE reduces the input loading of the DFE by embracing the RZ sampler output instead of the conventional NRZ output, which adds to the delay associated with an RS latch. A prototype chip fabricated in 40-nm CMOS technology consists of an analog front-end (AFE), a phase rotator (PR), a current digital-to-analog converter (DAC), and synthesizable digital logic (SDL), occupying a total active area of 0.24 mm 2. The proposed PAM-4 receiver achieves a bit-error rate (BER) of less than 10 −11 at 48 Gb/s and offers an energy efficiency of 2.42 pJ/b.