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A Cryo-CMOS PLL for Quantum Computing Applications
本文提出了一种用于量子计算控制的4.2K低温CMOS PLL。
40nm CMOS, 4.2K, 10GHz, 37fs rms jitter, -69dBc参考杂散, 2.7mW功耗
低温CMOSPLL量子计算相位噪声动态放大器
▸创新点1：首次实现4.2K低温PLL，填补了量子计算控制系统中低温PLL的空白，为量子计算机的扩展性控制提供了关键技术支持。
▸创新点2：采用动态放大器电荷域子采样相位检测器（PD），通过高相位检测增益和最小化对VCO控制的周期性干扰，实现了低相位噪声和低参考杂散。
▸创新点3：设计了专用的模拟PLL结构，确保在300K到4.2K的温度范围内保持高性能，解决了低温环境下电路性能下降的难题。
▸创新点4：在40nm CMOS工艺下实现了高性能PLL，在300K时达到-78.4dBc参考杂散和75fs rms抖动，4.2K时抖动降至37fs，功耗仅为2.7mW。
Abstract
This article presents the first cryogenic phase-locked
loop (PLL) operating at 4.2 K. The PLL is designed for the
control system of scalable quantum computers. The specifications
of PLL are derived from the required control fidelity for a single-
qubit operation. By considering the benefits and challenges of
cryogenic operation, a dedicated analog PLL structure is used
so as to maintain high performance from 300 to 4.2 K. The
PLL incorporates a dynamic-amplifier-based charge-domain sub-
sampling phas