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A Differential Flip-Flop With Static Contention-Free Characteristics in 28 nm for Low-V oltage, Low-Power Applications
28nm CMOS工艺下静态无竞争差分触发器，适用于低电压低功耗应用。
28nm CMOS, 1-0.3V, 100 dies functional at 0.28V
差分触发器低功耗静态无竞争28nm CMOS低电压
▸创新点1：静态无竞争操作（方法创新）。采用脚位差分锁存器设计，消除了传统传输门触发器中的冗余内部时钟转换，实现了完全静态且无竞争的操作，显著提高了电路的稳定性和可靠性。
▸创新点2：低电压高容差（电路创新）。通过优化电路结构，在低至0.3V的电源电压下仍能保持高容差性能，支持1-0.3V的宽范围电压可扩展性，适用于超低功耗应用场景。
▸创新点3：功耗降低64%/56%（性能创新）。在1V电源电压下，相较于传统传输门触发器，静态功耗降低64%，动态功耗降低56%，显著提升了能效比，尤其适合高能效要求的应用。
▸创新点4：工艺兼容性与高良率（系统创新）。在28nm CMOS工艺下实现，所有100个测试芯片在五个工艺角下均能正常工作，最低工作电压低至0.28V，展示了优异的工艺兼容性和高良率特性。
Abstract
A static contention-free differential flip-flop (SCDFF) is presented in 28-nm CMOS for low-voltage and low-power applications. The SCDFF offers fully static and contention-free operation without redundant internal clock transitions with footed differential latches and the same area as a conventional transmission-gate flip-flop (TGFF). The fully static and contention-free operation allows high variation tolerance at a low supply voltage regime, achieving wide-range voltage scalability (1–0.3 V). The measurement results with a test chip fabricated in 28-nm CMOS technology show that power consumption is reduced by 64%/56% with a 0%/10% activity ratio at 1 V compared to that of a TGFF. All 100 dies from five process corners were functional with supply voltage as low as 0.28 V .