Beyond Eliminating Timing Margin An Efficient and Reliable Negative Margin Timing

Abstract

Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess timing margin but suffer from miss detection risk due to inactivation of the critical paths. We propose a negative margin timing error detection (NMED) method to increase detection reliability, which further pushes the timing margin to beyond eliminating it, by monitoring less critical yet often activated paths instead of the most critical but rarely activated paths. To further reduce its area overhead,