In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and

Abstract

Computing in-memory (CIM) is a promising new computing method to solve problems caused by von Neumann bottlenecks. It mitigates the need for transmitting large amounts of data between the processing and memory units, significantly decreasing the latency and energy consumption. However, writing back the calculation results for CIM can become a new bottleneck if only parallel computing is implemented. This study proposes a bidirectional static random access memory (SRAM) array structure comprising self-cycling eight-transistor (8T) cells, which can achieve full-array Boolean logic operations and read/write in two directions. The CIM results can be restored in in situ bit cells in a single cycle without additional memory. In addition, any data row can be copied into another row by controlling the intermediate transistor in the 8T cell. A 16-kb SRAM was implemented in the 28-nm CMOS technology to verify the effectiveness of the proposed design. The throughput of the proposed CIM macro is 1851.4 GOPS. Compared with the existing CIM macros, the throughput increased 3–56.6 times and the energy efficiency was as high as 270.5 TOPS/W at a supply voltage of 0.66 V . When the proposed circuits were applied to advanced encryption standard (AES) algorithms, the energy efficiency is increased by about 47.5%–63% compared to the von Neumann architecture.