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PLL Fractional Spurs Impact on FSK Spectrum and a Synthesizable ADPLL for a Blue
本文提出了一种用于蓝牙低能耗发射器的全数字锁相环设计,通过新型时间数字转换器和校准方案降低分数杂散。
频率范围1.8–2.7 GHz,功耗3.91 mW@2.4006 GHz,FoM -220.7 dB
全数字锁相环蓝牙低能耗分数杂散时间数字转换器数字校准
▸新型两段式时间数字转换器(TSTDC)
▸嵌入式TDC与Vernier延迟线TDC结合
▸数字校准方案补偿非线性
Abstract
In this work, we present an open-source fully-
synthesizable fractional-N all-digital phase-locked loop (ADPLL)
designed for a Bluetooth low-e nergy (BLE) transmitter (TX)
along with a semi-analytical model of the PLL fractional spur’s
impact on the BLE output spectrum. Based on the model and
the BLE specification for spur emission, a requirement for the
PLL fractional spurs is derived. To meet the derived spectral
mask by reducing the fractional spurs, a novel synthesizable
two-step time to digi