PLL Fractional Spur’s Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter Kyumin Kwon , Student Member , IEEE,O m a rA .B .A b d e l a t t y, Student Member , IEEE, and David D. Wentzloff , Senior Member , IEEE

Abstract

In this work, we present an open-source fully- synthesizable fractional-N all-digital phase-locked loop (ADPLL) designed for a Bluetooth low-e nergy (BLE) transmitter (TX) along with a semi-analytical model of the PLL fractional spur’s impact on the BLE output spectrum. Based on the model and the BLE specification for spur emission, a requirement for the PLL fractional spurs is derived. To meet the derived spectral mask by reducing the fractional spurs, a novel synthesizable two-step time to digital converter (TSTDC) that employs embed- ded TDC (EMBTDC) as coarse and Vernier delay-line TDC (DLTDC) as fine TDC is proposed. We also present a digital calibration scheme to compensate for the nonlinearity induced by the place-and-route (P&R) tool. The PLL is fabricated in 12-nm FinFET and demonstrated in a BLE-TX. The measured BLE transmissions satisfy the standard requirements thanks to the reduced fractional spurs. In a standalone PLL mode, the proposed TSTDC and calibration scheme reduced the fractional spurs by 14.3 dB compared to only using an EMBTDC in near- integer N operation. The PLL supports a frequency range of 1.8–2.7 GHz and consumes 3.91 mW at 2.4006 GHz achieving figure of merit (FoM) of −220.7 dB in fractional-N mode with a 40 MHz reference, occupying an area of 0.063 mm 2.Ah i g h l y automated design flow is used for the PLL to lower the barrier for new developers and reduce the porting cost.