← 返回 JSSC 论文列表JSSC 2023第6期Data Converters55nmDelta-Sigma ADC
A 12-V 287- μW 940-dB SNDR Discrete-Time 2-0 MASH Delta-Sigma ADC Lingxin Meng Y
一种低功耗高精度的12V 2.87μW 94.0dB SNDR离散时间2-0 MASH ΔΣ ADC
55nm CMOS, 12V, 2.87μW功耗, 94.0dB SNDR, 96.9dB动态范围, 1kHz带宽, OSR=125
ΔΣ ADC多级噪声整形低功耗高精度动态体偏置
▸采用全动态2-0多级噪声整形(MASH)架构
▸使用3位异步逐次逼近寄存器(SAR)ADC实现前馈数字电路并复用为零阶后端级
▸动态体偏置(DBB)技术提升单级浮动逆变放大器(FIA)增益
Abstract
This article presents a fully dynamic 2-0 multi-
stage noise-shaping (MASH) analog-to-digital converter (ADC)
for low-power and high-precision applications. It implements
the feedforward digitally with a 3-bit asynchronous successive-
approximation-register (SAR) ADC and reuses it as the zeroth
backend stage. Correlated level shifting (CLS) boosts the floating
inverter amplifier (FIA) gain, embedded in the loop filter to
implement integration. Dynamic body-biasing (DBB) technique
helps boost the ga