JSSC 2023第6期Clocking & PLLs28nmPLL

A 20-GHz PLL With 209-fs Random Jitter Yu Z h a o Member IEEE Mahdi Forghani

一款20GHz整数N分频PLL，采用双沿采样相位检测器和新型反馈分频器重定时方法，实现209fs随机抖动。

28nm CMOS, 20.9fs rms抖动(10kHz-40MHz), -66dBc杂散, 12mW功耗

锁相环相位噪声随机抖动CMOS整数N分频

▸相位检测器采样参考时钟的上升和下降沿

▸反馈分频器中采用新型重定时方法

▸针对参考和振荡器相位噪声优化

Abstract

This article describes an integer- N phase-locked loop (PLL) that incorporates a phase detector sampling both the rising and falling edges of the reference clock. The circuit also uses a new retiming method in the feedback divider . Optimized for the reference and oscillator phase noise and fabricated in the 28-nm CMOS technology, the experimental prototype achieves an rms jitter of 20.9 fs integrated from 10 kHz to 40 MHz with a spur level of −66 dBc while consuming 12 mW of power .