JSSC 2023第6期Clocking & PLLs40-nmPLLNeural Network Accelerator

A Low-Spur Fractional-N PLL Based on a Time-Mode

介绍了一种基于时间模式算术单元的低抖动、低杂散分数N锁相环。

182-fs rms jitter, 3.5-mW power consumption, worst fractional spur below −59 dBc

分数N锁相环时间模式算术单元低抖动低杂散CMOS

▸创新点1：采用时间模式算术单元（TAU）进行相位误差提取，这是一种新型的时间信号处理器，能够计算输入时间偏移的加权和，从而有效提取DCO相位误差，显著降低了杂散水平。

▸创新点2：低抖动设计，通过优化TAU和DCO的协同工作，实现了182-fs rms抖动的高性能指标，同时功耗仅为3.5-mW，展现了高效的电路设计。

▸创新点3：无需背景校准即可保持低杂散，即使在电源或温度变化较大的情况下，最差杂散仍低于-51.7 dBc，体现了系统的鲁棒性和稳定性。

▸创新点4：在40-nm CMOS工艺下实现，展示了该设计在先进工艺节点下的可行性和高性能，为未来集成电路设计提供了参考。

Abstract

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (T AU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs—the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges—and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below −59 dBc. Under considerable supply or temperature variations, the worst spur still remains below −51.7 dBc without any background calibration tracking.