← 返回 JSSC 论文列表JSSC 2023第6期Digital Circuits40nm
An Energy-Efficient Doubl e Ratchet Cryptographic Processor With Backward Secrecy
首款支持双棘轮协议且具备后向保密性的物联网节能加密处理器
40nm CMOS, 0.56V, 16MHz, 1.03mm², 227k gates, 1.18mW
双棘轮协议后向保密物联网安全节能加密硬件加速
▸采用基于预计算的恒定模分频器，面积减少39.5%，能耗降低18.8%
▸提出基于哈希的密钥派生函数模块，长度选择器能耗降低89.8%，模块总能耗减少35%
▸共享1字节S-box用于密钥生成和文本加解密，面积减少46.8%
Abstract
This work presents the first cryptographic processor
that supports the double ratchet protocol with backward secrecy
for the Internet-of-Things (IoT) devices. A precomputation-
based constant modular divider is used to reduce the area by
39.5% and energy consumption by 18.8%. A hash-based key
derivative function (HKDF) module is proposed to reduce the
energy consumption of the length selector by 89.8% and the
energy consumption of the module by 35% by leveraging
the characteristic of the input. A