Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting

Abstract

This article proposes a cryogenic inverter-based low noise amplifier (LNA) for qubit readout. Its input impedance matching is realized by a high- Q ON-chip gate inductor and capacitive load through the gate-to-drain feedback capacitance of the input transistors. Cascode transistors are used to optimize the impedance matching, which results in a larger gate inductor and smaller load capacitor and hence a higher passive and inverter gain. Owing to the high passive gain and Q-factor of the gate inductor at 4 K, the noise of the active stages is substantially sup- pressed with a negligible noise contribution of the gate inductor. Moreover, with the current re-use in the inverter topology, less power consumption is achieved for the given transconductance of transistors. The input impedance, gain, and noise analyses of the proposed LNA are performed for room temperature (RT) operation, and its noise optimization is done by taking the cryogenic operation of the devices into account. We demonstrate with the circuit analysis and measurement results that the input impedance of the LNA has a low sensitivity to variations on device parameters at cryogenic temperatures. The LNA is implemented in a 28 nm CMOS technology. It achieves 0.4–0.7 dB noise figure (NF) with 4.2 mW power consumption at 4 K, and its operating frequency is between 6–8 GHz. The LNA consumes very low power compared to the state-of-the-art cryogenic CMOS LNAs while providing similar NF performance at 4 K, which makes it s