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Improving Linearity in CMOS Phase Interpolators Amit
提出一种改进线性度的CMOS相位插值器，采用积分模式实现高相位线性度。
13.3 GHz, 9-bit分辨率, 6-mW功耗, 0.006 mm²面积
相位插值器CMOS线性度低功耗finFET
▸创新点1：积分模式相位插值器 - 该方法通过集成相移加权电流源生成高相位线性度的电压斜率，显著提高了相位插值器的线性度，支持高速和低功耗操作。
▸创新点2：双边缘插值技术 - 该技术实现了双边缘插值，改善了占空比失真特性，提高了输出时钟的精度和稳定性。
▸创新点3：低功耗设计 - 采用0.75V 5nm FinFET技术，通过堆叠器件创建电流源/汇，实现了低功耗设计，在14GHz频率下仅消耗6mW功率。
▸创新点4：高性能指标 - 该相位插值器在13.3GHz频率下实现了9位分辨率的输出时钟，峰值积分非线性度（INL pp）和峰值差分非线性度（DNL pp）分别为2.4°和1.4°，随机抖动仅为71-fsrms，动态线性度测量中集成了-42.6 dBc的旋转杂散。
Abstract
We compare the prior art in phase interpola- tors (PIs), classifying them as current-mode, voltage-mode, and integrating-mode PI. Next, we present an integrating-mode PI where the voltage slopes with high phase linearity are gener- ated through the integration of phase-shifted weighted current sources. The constant and variable voltage slopes are generated by current sources/sinks created using stacked devices in a 0.75-V 5-nm finFET technology. This PI technique supports the high-speed and low-power operation and achieves dual-edge interpolation with improved duty-cycle distortion characteristics. The PI generates an output clock with 9 bits of resolution and a small peak-to-peak integral nonlinearity (INL pp) and peak-to-peak differential nonlinearity (DNL pp) of 2.4 ◦and 1.4 ◦, respectively, at 13.3 GHz with just quadrature clock inputs. The PI has a 71-fsrms random jitter (integrated from 3 MHz to 3 GHz) and occupies an active area of 0.006 mm2 while consuming 6-mW power at 14 GHz. An integrated rotation spur of −42.6 dBc for 256-ppm modulation at 13.3-GHz operating frequency is achieved for 1-GHz update rate for the dynamic linearity measurements.