JSSC 2023第7期Data Converters40nmSAR ADCNeural Network Accelerator

A 1-GSs 68-b Cryo-CMOS SAR ADC for Quantum Computing Gerd Kiene

一款用于量子计算的1GS/s 68位低温CMOS SAR ADC，支持多通道频率复用输入。

40nm CMOS, 1GS/s, 6-8位分辨率, 36.2dB SNDR, 200pJ/conv-step FOM

量子计算低温CMOSSAR ADC频率复用自旋量子位

▸创新点1：两倍交织循环展开SAR ADC（系统创新）。该设计采用双通道交织技术和循环展开结构，实现了1 GS/s的高采样率，同时保持6-8位分辨率，显著提升了量子计算中多通道频率复用信号的数字化效率。

▸创新点2：改进的共模切换方案（电路创新）。针对低温环境下器件行为的变化，优化了共模切换策略，确保在4.2 K下ADC的稳定性和性能，实现了36.2 dB的SNDR和200 pJ/conv-step的FOM。

▸创新点3：灵活的校准机制（方法创新）。通过动态校准技术补偿低温导致的器件参数漂移，支持多通道同步校准，使ADC在宽温范围内（300 K至4.2 K）保持高精度，核心功耗仅0.8 mW。

▸创新点4：低温CMOS集成（工艺创新）。采用40 nm CMOS工艺实现低温兼容设计，功耗低至0.5 mW/量子比特，为大规模量子处理器集成了低温读出模块。

Abstract

This article presents a two-times interleaved, loop- unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6–8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry read- out for quantum computing. To optimize the circuit for the altered device behavior at cryogenic temperatures, a modified common-mode switching scheme is adopted as well as a flexible calibration.