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A 7-nm FinFET 1.2-TB/s/mm 2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded
7纳米FinFET工艺下开发的3D堆叠SRAM模块，采用电感耦合技术实现低功耗高速通信
0.7 pJ/bit, 8.5 Gb/s/link, 1.2-TB/s/mm2
3D堆叠SRAM电感耦合FinFET低功耗
▸创新点1：新型物理布局方法减少磁场衰减（方法创新）。通过优化线圈放置位置，使其能够覆盖现成的SRAM宏单元，同时最小化磁场衰减，从而提高了无线通信的效率。
▸创新点2：曼彻斯特编码同步通信（系统创新）。采用曼彻斯特编码实现同步通信，确保数据传输的准确性和稳定性，尤其是在高速数据传输场景下表现优异。
▸创新点3：时钟比较器检测小摆幅信号（电路创新）。引入时钟比较器技术，能够有效检测和处理小摆幅信号，提高了信号检测的灵敏度和可靠性。
▸创新点4：4层3D堆叠SRAM模块（系统创新）。通过采用4层3D堆叠技术，实现了1.2 TB/s/mm²的面积效率，相比现有技术提升了两个数量级。
Abstract
A 0.7-pJ/bit, 8.5-Gb/s/link inductive coupling inter- chip wireless communication interface for a 3D-stacked static- random access memory (SRAM) has been developed in a 7-nm FinFET process. A new physical placement method that allows coils to be placed over off-the-shelf SRAM macros with small magnetic field attenuation, together with the use of synchronous communication using Manchester encoding and a clocked com- parator to enable the detection of small-swing signals, achieves a 26% reduction in SRAM die area compared to through- silicon via (TSV)-based stacking. Interchip communication at 0.7 pJ/bit, 8.5 Gb/s/link was confirmed using test chips. A 4-hi 3D-stacked SRAM module using the proposed interface achieves a 1.2-TB/s/mm 2 area efficiency, representing a two orders-of- magnitude improvement over the state-of-the-art 3D-stacked SRAM.