Chip-to-Chip Interfaces for Large-Scale Highly Configurable mmWave Phased Arrays

Abstract

This article presents a chip-to-chip (C2C) interface for constructing reconfigurable phased arrays to be used in fifth-generation (5G)/sixth-generation (6G) wireless systems. The C2C interface further facilitates building phased array panels by allowing the use of grid-based PCB routing, thus providing flexibility in the system design. An eight-element RFIC capable of handling two independent data-streams is fabricated using 45-nm CMOS technology. The RFIC incorporates four C2C interfaces operating at 27 GHz, two C2C interfaces operating at 9 GHz, and a complex baseband (BB) with single-sided bandwidth in excess of 400 MHz. The architecture is tested by flip-chip bonding two fabricated RFICs on an eight-layer Megtron 7 PCB. In this article, only the receiver path of the RFIC and the phased array is described. Performance of both the single RFIC and the combination using the 27-GHz C2C interface is demonstrated using conductive and over-the-air (OTA) measurements. OTA measurements are conducted using 5GNR FR2 OFDM waveforms with a signal bandwidth of up to 800 MHz. The measured RF to BB conversion gain for a single element is larger than 23 dB and the minimum measured noise figure (NF) is 6.2 dB. The nominal dc power consumed by the receiver per element per stream is 116.5 mW. The RFIC occupies a normalized area per element per data stream of 2.7 mm 2. The RFIC is capable of supporting dual-polarized antennas or in a large-scale panel utilizing the same antenna elements to two