Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM b

Abstract

An effective design is proposed to reduce dynamic power consumption for a common clock synchronous two-read/ write (2RW) dual-port (DP) 8T static random access memory (SRAM). A self-adjusting wordline (WL) pulse timing control circuit is newly introduced for read/write operations. Row address inputs of ports A and B are compared in each cycle to detect the same row access or not. In the same row access from both ports, the disturbance should happen, which is an inherent mode of 2RW DP 8T SRAM. T