← 返回 JSSC 论文列表JSSC 2023第8期RF & Wireless45nm SOI CMOS
A 022 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving
一种基于时间交错多级开关电容的0.2-2 GHz可编程射频延迟元件，实现百纳秒级宽带延迟。
45nm SOI CMOS, 1V, 0.2-2GHz, 2.55-448.6ns可编程延迟, <0.12%延迟变化, 2.42ns延迟步进, 330ns/mm2面积效率, 26dB增益, 7.4dB噪声系数, 74mW功耗
射频延迟开关电容时间交错宽带可编程延迟
▸采用时间交错多级开关电容（TIMS-SC）技术实现百纳秒级宽带射频延迟
▸通过多级开关电容存储单元实现采样时间扩展
▸在宽温度范围内延迟变化极小，增益变化小于0.25 dB
Abstract
Simulation of radar returns, full-duplex systems,
and signal repeaters require hundreds of ns of programmable
broadband radio frequency (RF) delay in the signal path to
simulate large distances in the case of radar returns, for signal
cancellation in full-duplex, and for isolation from reflections
in signal repeaters. However, programmable broadband RF
delay has been limited to ones of ns due to challenges in
miniaturization with low loss and low power consumption. In this
work, we present a 0.2