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A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation Onur Memioglu
一款采用异质结架构的300GHz CMOS接收器，集成三个PLL以缓解相位失配问题。
28nm CMOS, 噪声系数16-20dB, 增益17-21dB, 1dB压缩点-17.3dBm, 270GHz PLL相位噪声-105dBc/Hz@10MHz
300GHz接收器CMOS相位锁定环异质结架构毫米波
▸采用270GHz和27GHz双本振异质结架构
▸集成三个片上PLL生成本振相位
▸在28nm CMOS工艺下实现低噪声和高增益
Abstract
A fully integrated receiver employs a heterodyne
architecture with 270- and 27-GHz local oscillators to alleviate
phase mismatch issues. The system incorporates three on-chip
phase-locked loops (PLLs) to generate the local oscillator phases
for both downconversions. Realized in 28-nm CMOS technology,
the prototype exhibits a noise figure of 16–20 dB, a gain of
17–21 dB, and a 1-dB compression point of −17.3 dBm. The
phase noise (PN) of the 270-GHz PLL is −105 dBc/Hz at 10-MHz
offset, amounting t