A 38-GSs 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Ou

Abstract

Efficient time-interleaved (TI) analog-to-digital con- verters (ADCs) that operate at high sample rates with wide input bandwidths are necessary to support increasing wireline transceiver data rates. This article presents a 7-bit 38-GS/s 32-way TI ADC that utilizes an eight-way interleaver archi- tecture based on a speed-enhanced bootstrapped switch that increases input bandwidth. ADC sample rate and efficiency is improved with pipelined-successive approximation register (SAR) unit ADCs that emp