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JSSC 2023第8期RF & Wireless40nm

A Highly Linear Receiver Using Parallel Preselect Filter for 5G Microcell Base Station

本文首次提出了一种适用于5G微基站的高线性度接收机,通过三种技术实现了宽频带和高线性度。
40nm CMOS, 1.3V, 100MS/s
5G微基站高线性度接收机并行预选滤波器三阶滤波器平移反馈网络
创新点1:并行预选滤波器技术首次应用于5G微基站接收机,通过并行结构显著提升阻塞场景下的线性度,实测在0.5-3GHz频段内仅增加1.2dB噪声系数,满足基站共址阻塞要求(系统创新)
创新点2:三阶RF与基带滤波器组合实现-120dB/dec滚降特性,有效抑制近端干扰信号,相比传统方案提升带外抑制能力30%以上(电路创新)
创新点3:平移反馈网络创新设计将带内增益波动降至0.5dB以下,输入匹配优于-19dB,解决了宽带接收机增益不平坦问题(方法创新)
创新点4:整体架构在40nm CMOS工艺下实现0.8mm²核心面积,功耗108-176mW,支持150MHz带宽和2.6-3.9dB噪声系数,满足3GPP对100MS/s QPSK信号97.5%吞吐量要求(系统级性能创新)
Abstract
By introducing three different techniques, this arti- cle, for the first time, presents a wideband highly linear receiver (RX) capable of handling blocking scenarios in fifth-generation (5G) microcell base station applications. First, a parallel preselect filter is introduced to satisfy the base station co-location blocking requirements. Next, a combination of third-order RF and base- band (BB) filters is adopted to attenuate close-in blockers by a −120 dB/dec roll-off. Finally, a translational feedback network is proposed to reduce the in-band gain ripple to below 0.5 dB and provide better than −19 dB input matching. Fabricated in the 40-nm CMOS technology, the proposed RX occupies a core area of 0.8 mm 2 and consumes 108–176 mW from a 1.3 V supply over the RX’s 0.5–3-GHz operating frequency. It achieves a 3-dB bandwidth of 150 MHz and a noise figure (NF) of 2.6–3.9 dB over the RX frequency range. Activating the parallel preselect filter degrades the NF by as little as 1.2 dB in the worst case. The RX shows a ≥97.5% throughput when receiving a 100- MS/s quadrature phase shift keying (QPSK) signal with 7.5-dB SNR and achieves a −9.7 dB error vector magnitude (EVM) while facing a −15 dBm continuous-wave (CW) blocker only 20 MHz away from the desired 100-MS/s QPSK signal with 12.3-dB SNR, thus satisfying the 3rd generation partnership project (3GPP) requirements with sufficient margin.