← 返回 JSSC 论文列表JSSC 2023第8期Digital Circuits65nm
A Time-Domain Wavefront Computing Accelerator With a 32 32 Reconfigurable PE Arr
提出一种基于32×32可重构PE阵列的时域波前计算加速器，用于解决最短路径等问题。
65nm CMOS, 776 pJ per task
时域波前计算可重构PE阵列最短路径问题迷宫求解科学模拟
▸创新点1：时域波前计算方法创新，通过传播上升沿信号实现最短路径搜索，无需传统A*算法的距离计算或估计，显著降低计算复杂度，单次执行即可获得所有最优路径。
▸创新点2：可重构PE阵列架构创新，支持32×32规模的二维处理单元动态配置，可切换为King’s graph或lattice graph模型，适用于最短路径搜索、迷宫求解及科学模拟等多场景应用。
▸创新点3：高性能硬件实现创新，采用65nm工艺的1mm²测试芯片，在1.2V/1.0V核心电压下实现776pJ/任务能效及1.6G edges/s搜索速率，展现低功耗与高并行性优势。
▸创新点4：系统级应用扩展创新，通过单/多起点配置模拟圆形或平面波前传播，验证了该加速器在科学计算领域的潜力，拓展了传统图论算法的物理实现边界。
Abstract
This work presents a hardware accelerator realizing
true time-domain wavefront computing in a massive parallel two-
dimensional (2-D) processing element (PE) array. The proposed
2-D time-domain PE array is designed for multiple applications
based on its scalable and reconfigurable architecture. The short-
est path problem (a classical problem in graph theory) is one
of the critical problems to solve using the proposed accelerator.
Unlike the A
∗ search algorithm, a heuristic method widely used
in