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An 18-MS/s 76-dB SNDR Continuous-Time 16 Modulator Incorporating an Input V oltage Tracking GmC
提出一种高线性度连续时间16调制器,采用输入电压跟踪技术消除非线性。
18-MS/s, 76.5-dB SNDR, 93-dB SFDR, 3.21 mW
连续时间调制器高线性度GmC积分器电压跟踪FIR滤波器
▸采用输入电压跟踪技术实现高线性度
▸共享单反馈DAC优化架构
▸集成一阶FIR滤波器的源串联终止DAC
Abstract
This article presents a highly linear continuous- time (CT) 16 modulator incorporating energy-efficient open- loop GmC integrators with 1-V ppd full-scale (FS) voltage. The second-order loop filter is inherently linearized using an input voltage tracking technique. Here, the modulator input and digital to analog converter (DAC) feedback signal have the same linear and non-linear voltage to current conversion. Subtracted in the current domain in the Gm-stage, the non-linear contributors are eliminated and a highly linear wide-swing open-loop filter architecture is obtained. Linearity impairments due to tracking errors between the feedback DAC signal and the modulator input are analytically discussed and optimizations are introduced. The proposed 16 architecture takes advantage of a single feedback DAC which is shared among both the GmC integrators within the loop filter. A first-order finite impulse response (FIR) filter incorporated in the single feedback DAC is implemented by two 5-bit time-interleaved source-series terminated (SST) DACs comprising a data-dependent supply impedance compensation. Fabricated in a 22-nm FD SOI process, the 18-MS/s prototype consumes 3.21 mW combined from a 0.9- and 1.3-V power supply. Revealing 93-dB spurious free dynamic range (SFDR) at 76.5-dB peak signal to noise and distortion ratio (SNDR) performance, the prototype design achieves a 171-dB figure of merit (FoM) S with only 41-fF input capacitance.